1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor integrated circuit device and, more particularly, to a method for manufacturing a semiconductor integrated circuit device improved to prevent the situation in which a residue of a metal wiring remains on a step portion of an interlayer insulating film and this residue comes off during manufacturing step and contaminates a wafer surface and manufacturing facilities in a scribe line portion.
2. Description of the Background Art
Manufacturing steps of a semiconductor integrated circuit device comprise the step of cutting a chip formed on a wafer along a scribe line. FIG. 3 is a plan view of a wafer on which a plurality of chips of a semiconductor integrated circuit are formed. Referring to FIG. 3, a plurality of chips 2 of a semiconductor integrated circuit device are formed on a wafer 1. The plurality of chips 2 are each separated by a scribe line. FIG. 4 is an enlarged view of an A portion in FIG. 3. Referring to FIG. 4, the chip 2 comprises a device forming portion 4 and a contact portion 5 with an external electrode (hereinafter referred to as a pad portion 5). Needless to say, any device, insulating film, metal wiring or the like is not provided in the portion of the scribe line 3, so that the surface of the semiconductor substrate is exposed. The chips 2 are each separated by a scriber along this scribe line 3.
Focusing on the scribe line portion, a description is given of conventional manufacturing steps of a semiconductor integrated circuit device.
FIGS. 5A to 5J are partially sectional views of a semiconductor integrated circuit device showing conventional manufacturing steps. In these figures, only a scribe line portion 3, a pad portion 5 and a device forming portion 4 are described.
Referring to FIG. 5A, an oxide film 7 for separating devices is formed on a main surface of a semiconductor substrate 6 on which the scribe line portion 3 is to be formed. A MOSFET comprising a device 15, for example, a gate electrode 8 is formed on an active region between the oxide films 7. Then, an external electrode 9 (hereinafter referred to as a pad 9) is formed on the oxide film 7 for separating devices. Thereafter, a first interlayer insulating film 10 is formed on the whole surface of the semiconductor substrate 6 comprising the gate electrode 8 and the pad 9.
Referring to FIG. 5B, a contact hole 11 is provided in the first interlayer insulating film 10 by photolithography and etching, for example in order to expose the source and drain regions of the MOSFET. At the same time, the first interlayer insulating film 10 in the scribe line portion is etched away in order to expose the scribe line portion 3 of the semiconductor substrate 6. A step portion 12 of the first interlayer insulating film is formed in the scribe line portion 3 by etching away the first interlayer insulating film 10 in the scribe line portion 3. Then, a first metal wiring film 13 is formed on the whole surface of the semiconductor substrate 6 comprising the step portion 12 of the first interlayer insulating film and the contact hole 11.
Referring to FIGS. 5B and 5C, the first metal insulating film 13 is patterned to become a given configuration to form a pattern of a first metal wiring 16a electrically connected to the source and drain regions, and a first metal wiring 16b electrically connected to the pad 9. At this time, a residue 14 of the first metal wiring film remains on the step portion 12 of the first interlayer insulating film. Then, a second interlayer insulating film 17 is formed on the whole surface of the semiconductor substrate 6 comprising the residue 14 of the first metal wiring film and the first metal wiring 16.
Referring to FIG. 5D, the second interlayer insulating film 17 is formed on the whole surface of the semiconductor substrate comprising the residue 14 of the first metal wiring layer and the first metal wiring 16, and a first resist 18 is applied thereto. Then, the first resist 18 is patterned by photolithography so as to form on the first resist 18 openings in a portion over the scribe line portion 3 of the semiconductor substrate 6 and portions over the contact portions of the first metal wirings 16a and 16b (the portions on which contact holes 19a and 19b are to be formed). Thereafter, the second interlayer insulating film 17 is etched to form the contact holes 19a and 19b in the second interlayer insulating film 17, using this patterned first resist 18 as a mask. At this time, a step portion 23 of the second interlayer insulating film 17 is formed in the scribe line portion 3. Then, the first resist 18 is removed.
Referring to FIG. 5E, a second metal wiring film 20 is formed on the whole surface of the semiconductor substrate 6 comprising the contact holes 19a and 19b. Thereafter, a second resist 21 is applied onto the whole surface to pattern the second resist 21 such that a predetermined configuration having the upper portions of the contact holes 19a and 19b may be left.
Referring to FIGS. 5E and 5F, a second metal wiring 22a electrically connected to the first metal wiring 16a for connecting to the source and drain, and a second metal wiring 22 electrically connected to the first metal wiring 16b for connecting to the pad are formed by patterning the second metal wiring film 20, using the pattern resist 21 as a mask and then removing the resist 21. When the second metal wiring film 20 is patterned, the residue 24 of the second metal wiring film is left on the step portion 23 of the second interlayer insulating film 17.
Referring to FIG. 5G, a third interlayer insulating film 25 is formed on the whole surface of the semiconductor substrate 6 comprising the residue 24 of the second metal wiring film and the second metal wirings 22a and 22b and then a third resist 26 is applied thereto. Then, the third resist 26 is patterned by photolithography so as to form openings at the portion of the scribe line portion 3 of the semiconductor substrate 6 and the portions on the second metal wirings 22a and 22b (the portion on which contact holes 27a and 27b are to be formed). Thereafter, the third interlayer insulating film 25 is etched using this patterned third resist 26 as a mask to form the contact holes 27a and 27b in the third interlayer insulating film 25. At this time, a step portion 28 of the third interlayer insulating film 25 is formed at the scribe line portion 3. Then, the third resist 26 is removed.
Referring to FIG. 5H, a third metal wiring film 29 is formed on the whole surface of the semiconductor substrate 6 comprising the step portion 28, the contact holes 27a and 27b. Then, a fourth resist 30 is applied to the whole surface and then patterned such that a pattern with a predetermined configuration comprising the upper portions of the contact holes 27a and 27b may be left.
Referring to FIGS. 5H and 5I, the third metal wiring film 29 is patterned using the patterned fourth resist 30 as a mask and then the fourth resist 30 is removed to form a third metal wiring 31a electrically connected to the second metal wiring 22a and a third metal wiring 31b electrically connected to the second metal wiring 22b. When the third metal wiring film 29 is patterned, a residue 32 of the third metal wiring film is left at the step portion 28 of the third interlayer insulating film 25.
Referring to FIG. 5J, a passivation film 33 is formed on the whole surface of the semiconductor substrate 6 and etched away so as to expose the scribe line portion 3 of the semiconductor substrate 6 and the pad portion of the third metal wiring 31b, and finally the wafer shown in FIG. 3 and 4 can be formed. The chips 2 are each separated by cutting the scribe line portion 3 with a scriber.
A method for manufacturing a conventional semiconductor integrated circuit device is structured as described above. Referring to FIGS. 5B, 5E and 5H, the first metal wiring film 13, the second metal wiring film 20 and the third metal wiring film 29 are usually formed by sputtering and the like. However, as devices are miniaturized, it is required that the step coverage of the metal wiring films 13, 20 and 29 should be improved. Therefore, as means for forming a metal wiring film, a method by bias sputtering, a method for preheating the semiconductor substrate 6 at the time of sputtering and a method by CVD are proposed at present to improve the step coverage. On the other hand, many cases use anisotropic etching such as reactive ion etching which is superior in processing controllability in etching the metal wiring films 13, 20 and 29. This reactive ion etching is a technique developed to meet the demand of the miniaturization of devices and it is indispensable means in manufacturing the present semiconductor integrated circuit device.
However, the following problem is raised when the metal wiring films 13, 20 and 29 having good step coverage is processed by anisotropic etching such as reactive ion etching which is superior in processing controllability to expose the surface of the semiconductor substrate 6 in the scribe line portion 3. That is, a film thickness of the metal wiring film 13 in the step portion 12 of the interlayer insulating film 10 is thicker than the plain portion of the scribe line portion 3 by a film thickness of the lower layer interlayer insulting film 10. For this reason, referring to FIG. 5C, when anisotropic etching method is used to selectively etch the metal wiring film 13 away, the undesirable residue 14 of the metal wiring film substantially remains at the step portion 12 of the interlayer insulating film 10. The higher and steeper the step portion of the interlayer insulating film of the lower layer is and the better the step coverage of the metal wiring film is and, further, the stronger the anisotropy of the anisotropic etching is, the more conspicuous the residue 14 of the metal wiring film at the time of etching is. Such a defect can be reduced by making thin and plain the interlayer insulating film of the lower layer to control the step portion of the interlayer insulating film of the lower layer. However, even if the interlayer insulating film of the lower layer was made thin and plain, it was not possible to perfectly prevent the metal wiring film from being left at the step portion of the interlayer insulating film in the scribe line portion 3 as long as anisotropic etching means was used. Since these residues 14, 24 and 32 of the metal wiring films remained thinly and long along the interlayer insulating films 10, 20 and 25, respectively, as shown in FIG. 5J, the adhesion with the semiconductor substrate 6 was relatively weak and the residue of the metal wiring film came off the step portion during the manufacturing step to contaminate a wafer surface or manufacturing facilities, causing a pattern defect in the semiconductor integrated circuit device.
As means for removing the residue of the metal wiring film, there is proposed a method for removing the residue of the metal wiring film completely by performing the anisotropic etching for more than usual time or a method for removing the residue of the metal wiring film by adding isotropic etching to this anisotropic etching. However, in the case of the former method, it is necessary to add a considerable long etching time, causing damage to the interlayer insulating film of the lower layer. In addition, it is necessary to make thick the resist used as a mask at the time of etching, causing another problem such as the reduction of the throughput. In case of the latter method, as a device is miniaturized, there are many disadvantages that the processing precision and control ability are lowered and a width of the metal wiring is reduced and the like.